Two primary elements in a computer are the processor and memory. However, the processor can execute instructions faster than the memory can deliver the data. Consequently, the processor is held up by the slowness of memory. To solve this problem, a cache is added to the main memory. The cache is a small memory which is much faster (but more expensive per byte stored) than ordinary memory. The cache holds blocks of data and supplies it to the processor.
After the processor finishes with the block held in the cache, the modified data will probably be returned to the main memory. However, this return operation can cause excess traffic on the data bus, as the sequence of FIGS. 1A-1D will explain.
Assume that the cache line of 16 bytes, located at the bottom in FIG. 1A, is to be returned. If the data bus is 4 bytes wide, then a single transfer is not possible; the transfer will require the sequence of four steps indicated in FIGS. 1A, 1B, 1C, and 1D. Four bytes are transferred in each step. During these four steps, the bus cannot be used for other operations. It is possible that this traffic on the bus is unnecessary, because some of the 16 bytes in the line may not have been modified, and do not require return to the memory.